# Idea Brief: HPT2 Personality Update Floor at 00-05-01

Status: exploring
Type: idea-brief
Updated: 2026-09-21
Next Action: plan SMI 00-05-01 implementation in this repository; bench transition testing remains paused
Readiness Review: run explicitly with ts: bs review; ordinary brainstorming does not review
Produces:

## Current Synthesis

### Idea

Release SMI 00-05-01 with an update guard that prevents an HPT2 unit from installing older FAT32-era personality firmware. Use the existing IMX header Title, firmware version, embedded image name, MachineMask, layout, and CRC checks. No new header field is required. SMI accepts a FAT32 DisplayTest handoff and performs the unit's controlled HPT2 initialization.

### Why It Matters

Controller B running older DisplayTest showed a persistent white screen with HPT2 media. It booted after the expendable card was formatted FAT32. A downgrade from HPT2 personality firmware to FAT32-era firmware could leave an installed controller without display access. Published SMI 00-05-00 supports HPT2 but does not have this guard; a new release is required.

### Desired Outcome

- SMI 00-05-01 identifies the candidate from its IMX header before any QSPI erase: numeric version parsed from Title, personality family from Title and embedded image name, intended machine from MachineMask, and existing integrity/layout checks.
- Admit recognized approved HPT2-capable SMI, CVO, or DVO personality images only at 00-05-01 or later. Reject older, unknown, inconsistent, or unparseable personality identities before erase and leave firmware bootable and SD media untouched.
- The common cutoff intentionally refuses reinstalling SMI 00-05-00, despite that release's HPT2 logger.
- SMI accepts eligible FAT32 media from the DisplayTest fixture, explicitly initializes HPT2 during unit production, and verifies logging, retention, history, and export. Already ready HPT2 media is not needlessly reinitialized.
- Prove forward installation from old and revised FAT32 DisplayTest handoffs, then prove legacy IMX rejection from guarded SMI without erase or boot loss.

## Constraints And Non-Goals

- CVO and DVO 00-05-01 will need their own HPT2-capable builds and proof; this lane implements SMI only.
- DisplayTest uses a separate 01-xx version series. Decide explicitly which DisplayTest images, if any, are admissible from guarded SMI; unknown images default to refusal.
- MachineMask alone does not establish product identity or SD compatibility. The version convention depends on controlled release discipline, not cryptographic authentication.
- Preserve published IMX files unchanged. Do not erase card data requiring retention without controlled disposition.
- This brief authorizes no code change, build, programming, format, power cycle, bench test, release, or rollout. Transition testing is paused.

## Shared Transition Contract

- DisplayTest normal production testing and Prep for Ship hand off verified FAT32 media; separate card-family qualification remains HPT2.
- Personality releases SMI, CVO, and DVO 00-05-01 and later signify HPT2 support.
- SMI 00-05-01 owns the controlled FAT32-to-HPT2 conversion and forward-only updater guard.
- Use separate project-bound Codex VS Code lanes. Related DisplayTest brief: FAT32 Production SD Handoff and Separate HPT2 Qualification in E:\dev\high_point\7520708_DispTest_FW.

## Open Questions

- Which DisplayTest 01-xx images may be installed from guarded SMI?
- Which exact released IMX specimens and target checks prove parsing, refusal before erase, and FAT32-to-HPT2 acceptance on both controller assemblies?

## Decisions

- Use existing IMX header information and the common 00-05-01 personality minimum.
- Fail closed on unknown or inconsistent identity before erase.
- Fixture handoff remains FAT32; SMI performs HPT2 conversion.
- Bench testing remains paused until the owner resumes it.

## Exploration Log

### 2026-09-21

- Owner selected a common 00-05-01 minimum for SMI, CVO, and DVO HPT2 personalities, directed the next SMI revision to be 00-05-01, and requested separate Tool Shed entry points.