# HPT graph rolling-cache correction

Status: baseline complete — exact image programmed and live scalar-read timing captured on both controls; final review follows bulk-read optimization
Type: evidence
Date: 2026-07-25
Updated: 2026-07-26
Timezone: America/Los_Angeles
Next Action: none; the optimized cumulative candidate passed the final A/B Graph/export review in work/evidence/candidate-identity-and-operator-graph-export-review-20260726.md
Campaign Reason: Historical record from campaign 013-close-hpt-media-2-initial-release-qualification; retained independently after campaign closure and requires no separate owner-queue execution.
Campaign: standalone
Parent: work/wp/completed/wp-correct-hpt-graph-rolling-cache-refresh.md

## Scope

This evidence covers the graph rolling-cache source correction, focused
regression checks, clean managed Debug build, packaging, exact-image
programming on both controls, and live post-reset readiness baselines. It does
not claim that the operator graph-screen checks have passed.

## Implemented behavior

- Graph entry uses the completed stable RAM cache and performs no media request
  or blocking sleep.
- An open graph no longer requests a full media traversal every 60 seconds.
- Each successfully persisted `STRT` or `EVNT` record is published into the RAM
  cache after the HPT append succeeds.
- Cache mutation and rendering retain the odd/even
  `gChartDataSequence` publication contract.
- A normal midnight boundary shifts the fixed 30-day window in RAM.
- Startup, new-media initialization, clock discontinuity, and invalid cache
  state retain a bounded full rebuild.
- Startup traversal retains each lane's recovered oldest/current segment range
  and advances one physical segment cursor per lane. A sequence outside a
  lane's retained range is rejected without scanning every segment.
- Service 468 shows total cache time, traversal time, and scanned/selected
  record counts from a coherent target-visible status block.
- The 30-day plus one-day/five-second chart geometry is unchanged.

## Software gates

| Gate | Result |
| --- | --- |
| `script/check-hpt-graph-cache.ps1` | PASS, `12/12` |
| `script/test-hpt-graph-cache-model.py` | PASS |
| `script/check-graph-data-policy.ps1` | PASS, all source and boundary-model checks |
| `script/check-hpt-commissioning.ps1` | PASS, `94/94` |
| `script/test-hpt-triple-circular-model.py` | PASS, exact split-lane `767/767/852`; zero missing-copy header reads |
| `script/check-version5-hpt-only-sd.ps1` | PASS, `11/11` |
| `script/check-hpt-customer-export.ps1` | PASS, `20/20` |
| `script/check-hpt-full-address-scrub.ps1` | PASS, `9/9` |
| `script/check-code-review-mitigations.ps1` | PASS, `15/15` |
| All repository `script/check-*.ps1` suites | PASS, `18/18` suites |
| `git diff --check` on graph source/check changes | PASS |
| Clean managed Debug rebuild | PASS |
| Production-name Debug packaging | PASS |

The clean build retained existing SSP/HMI warnings. No build-stopping
diagnostic was produced by the graph-cache change.

## Exact review artifact

- Firmware display version: `Version 00-05-00`
- Runtime update filename: `7520553_SMI_00_05_00.imx`
- Source base commit: `3af85b2311db42fc704066106ebf548cf6e05177`
- Source state: active working tree containing the graph-cache correction and
  the already-present post-freeze qualification changes; do not rebuild or
  substitute artifacts without recording new hashes
- Debug ELF:
  `Debug/7520553_SMI_FW.elf`
- Debug ELF SHA-256:
  `B3880827F7112C5799A882E1BC85D6B1994EDDB4AA34E0AB95817FEB9AE89A58`
- Debug S-record:
  `Debug/7520553_SMI_FW.srec`
- Debug S-record SHA-256:
  `EAD175B1F20D4E80858B69C4DCBC7A021125BDBE5EA6DD6B8E251ABCA681DA4B`
- Debug map:
  `Debug/7520553_SMI_FW.map`
- Debug map SHA-256:
  `89565FE38C0AB3EEFD4ADA24D2796086F721279DC583E0BCFCBA9DEF96300DDA`
- Packaged production-name files:
  `Debug/7520553_SMI_FW_00_05_00.{elf,srec,map}`
- Packaged files are byte-for-byte copies of the stable Debug artifacts.

## Program and live readiness

Both controls were programmed sequentially with the exact `EAD175B1...`
S-record. J-Link reported successful download, program/verify, reset, and run
on both probes.

Controller B was programmed and measured first. Its card was not formatted,
reinitialized, removed, or replaced. Controller A was then programmed with the
same hash-locked artifact.

| Field | Controller A | Controller B |
| --- | --- | --- |
| Assembly | `1751136` | `1751219` |
| J-Link | `69664082` | `69660123` |
| Program/verify/reset/run | PASS | PASS |
| S-record SHA-256 | `EAD175B1...81DA4B` | `EAD175B1...81DA4B` |
| Protocol card state | `6`, raw HPT | `6`, raw HPT |
| CID valid | `1`, valid | `1`, valid |
| Representative-sector read | `0`, success | `0`, success |
| HPT media state/status | `5 / 0`, ready/OK | `5 / 0`, ready/OK |
| System errors | `0` | `0` |
| Chart status | `3`, complete | `3`, complete |
| Chart publication sequence | `4`, stable/even | `4`, stable/even |
| Retained chart data | present | present |
| Initial cache load | complete | complete |
| Chart work units | `720/720` | `720/720` |
| Cache total time | `337 ticks`, `3.37 s` | `312 ticks`, `3.12 s` |
| Cache traversal time | `256 ticks`, `2.56 s` | `230 ticks`, `2.30 s` |
| Cache scanned/selected | `927 / 926` | `885 / 880` |
| Lane oldest sequence | `1 / 1 / 1` | `86 / 86 / 1` |
| Lane records at timed load | `927 / 927 / 927` | `800 / 800 / 885` |
| Retired segments | `0 / 0 / 0` | `2 / 1 / 0` |
| Graph cache ready | `true` | `true` |
| Logging completed/dropped at identity capture | `2 / 0` | `5 / 0` |

Controller B retained the intentional 85-record lane offset. Its lane-0 and
lane-1 oldest sequences are 86 while lane 2 starts at sequence 1; its two
shorter lanes therefore remain exactly 85 records behind the longer lane. The
new iterator skipped those absent historical copies from recovered range
metadata, so B completed faster than A despite the abnormal layout. No
redundant graph-entry traversal was requested.

### Controller A CID identity

- Manufacturer: SanDisk/WD
- MID: `0x03`
- OEM/application ID: `SD`
- Product: `SS08G`
- Revision: `8.0`
- Serial: `2540634244`
- Manufacturing date: `2024-05`
- Raw CID: `035344535330384780976F0084018559`
- Raw/live capture:
  `work/evidence/hpt-log-store-circular-mirror/controller-a/graph-cache-indexed-review-20260725/baseline/`
- Final readiness:
  `work/evidence/hpt-log-store-circular-mirror/controller-a/graph-cache-indexed-review-20260725/post-identity-readiness/chart-cache-status.json`

### Controller B CID identity

- Manufacturer: SanDisk/WD
- MID: `0x03`
- OEM/application ID: `SD`
- Product: `SS08G`
- Revision: `8.0`
- Serial: `2540634245`
- Manufacturing date: `2024-05`
- Raw CID: `035344535330384780976F0085018507`
- Raw/live capture:
  `work/evidence/hpt-log-store-circular-mirror/controller-b/graph-cache-indexed-review-20260725/preserved-split-lane/`
- Final readiness:
  `work/evidence/hpt-log-store-circular-mirror/controller-b/graph-cache-indexed-review-20260725/preserved-split-lane/post-identity-readiness/chart-cache-status.json`

## Operator review

Both controls are running the exact `EAD175B1...` S-record with the required
identity and readiness baselines above.

Cache timing is visible on service 468 as total/traversal seconds with the
scanned/selected counts. The normal graph control opens from Home using this
completed RAM cache.

For Controller A and Controller B, record:

- [ ] Graph opens promptly from Home without a data timeout and displays
  retained data.
- [ ] A newly completed production record appears while the graph remains open,
  without reopening the screen or requesting a media rescan.
- [ ] Zoom, pan, legend, and return remain usable.
- [ ] Graph export entry opens normally; cancel may be used before any export
  write if only screen/navigation review is intended.

Stop and investigate on a data-timeout message, empty retained view where data
is expected, unstable/flickering publication, missing new record, HPT/CID
identity change, new SD/HPT error, increased dropped-log count, watchdog/reset,
or unusable graph navigation.

## Disposition

Graph lifecycle implementation, build, exact-image A/B programming, and live
readiness gates are complete. This artifact now supplies the scalar
before-measurement for the active triple-mirror bulk-read workpackage. Final
graph/export acceptance is deferred until the optimized image is programmed
and measured on B then A.
