# Same-SMI image load and configuration preservation

Date: 2026-07-15  
Target: R7FS7G27H via J-Link serial 69664082

## Artifact

- SREC: `Debug/7520553_SMI_FW.srec`
- SREC SHA-256: `70CA38269672AAA433F567FCCDA39B36FBE430410B58E72F61156AEF00B88EBC`
- ELF SHA-256: `27FDB83684E92718A6AA745DBF2C440B316A3A9C9B91D8F7CAD7264098427DE2`

## Method

1. Captured the complete 4 KiB VEEPROM region at `0x40100000` before load.
2. Invoked J-Link `loadfile` with the exact qualified SREC.
3. J-Link compared both affected banks and reported `Skipped. Contents already
   match`; this test therefore exercised same-image verification and reboot, not
   a destructive code-flash rewrite.
4. Reset, ran for 15 seconds, captured the complete VEEPROM region again, and
   read live configuration and health state.

## Results

- Pre/post VEEPROM SHA-256:
  `01ABCD7D14A4753EE40199F09B1D0C3D851EE8F231EC31430DB5F02746076A51`
- Differing VEEPROM bytes: 0 of 4096.
- RAM and both blocks remained generation 5, model 5 (SMI7), Part ID `SLM722`.
- Configuration operational flag remained 1; semantic status remained all zero.
- RTD/effective temperature was 37.00055 C against the 37.0 C setpoint.
- Main control demand was active.
- Startup completed; main system errors were zero.
- SD remained available/READY with last status, I/O failures, mirror failures,
  and dropped-record count all zero.
- `RSTSR1 = 0x0004`, consistent with the commanded software reset.
- Controller was resumed and left running.

Result: PASS for same-image verification/reboot configuration preservation.
Actual code-flash rewrite coverage remains for a different-image or explicitly
erased/programmed transition test.
